With continuous development of information technology, mobile phones and other various electronic products become thinner and lighter. Mobile phones and computers have more and more functions while the size of which become smaller and smaller. Therefore, the requirement of the integration level of chips and devices becomes higher and higher. Along with the development of large-scale integration circuit, the integration level has reached an unprecedented level as the line width is approaching 22 nm. Meantime, more improvement of related technology and devices is also required. Since further reduction of line width becomes more and more difficult, the development of related technology process and devices therefore slows down.
In this case, 3D high density packaging technology has attracted widely attention, by which, no longer one chip but several chips can be packaged in one device. In addition, the chips are stacked into a 3D high-density assembled micro-chip rather than being arranged in the same layer. Hence, the 3D chip stacking greatly reduces the size of the device. Furthermore, the chip stacking process is also constantly developed. From FLIP CHIP technology to TSV (Through Silicon Via) through-hole interconnection technology, electronic devices become smaller and smaller. Package process is improved by technologies from the traditional bonding, chipping and plastic package to current essential processes such as RDL (Redistribution Layer), Flip Chip, wafer bonding, TSV and so on. Consequently, package structures with smaller sizes and higher chip density emerges continually.
By using the prior chip embedding technology, mass-production cannot be achieved efficiently due to the unreliability of heat dissipation. Especially for high-power devices, the application of chip embedded package is restricted by the heat dissipation management.